The present invention is directed to a cross-coupled latch. In particular, the latch circuit of the present invention is for use in a current mode controller for high frequency applications.
A typical cross-coupled latch is shown in FIG. 1. The latching circuit includes two cross-coupled switching transistors, 10 and 12. The collector of the first switching transistor 10 is connected to a first resistor 14 in series with a terminal 34 which receives the source voltage 34. The collector of the second switching transistor 12 is connected to a second resistor 16 which is connected in series with the voltage source terminal 34. A first cross-coupling resistor 18 is connected between the collector of the first switching transistor 10 and the base of the second switching transistor 12. A second cross-coupling resistor 20 is connected between the collector of the second switching transistor 12 and the base of the first switching transistor 10. The latching circuit is set by a setting circuit including resistor 26, resistor 28, and transistor 22. The resetting circuit includes resistor 30, resistor 32 and transistor 24.
In operation, a voltage greater than the base emitter voltage is applied to the reset pin at resistor 30. This will cause transistor 24 to conduct bringing the potential at the colector of the second switching transistor 12 to ground. With no base drive available, the first switching transistor 10 is turned off. Base drive current is now available to the second switching transistor 12 through the first resistor 14 and the first cross-coupling resistor 18. This current keeps second switching transistor 12 latched on. Even when the voltage at the reset pin is removed. The circuitry is symmetrical so that the same operation occurs when a voltage greater than the base emitter voltage is applied to the set pin at resistor 26. This will cause a reversal of the states of the switching transistors and switching transistor 10 will be latched on. This typical latching circuit is slow because of the time required to bring the switching transistors out of hard saturation. This makes this latching circuit inappropriate for high speed latching applications.
It is an object of the present invention to provide a latching circuit in which saturation of the switching transistor is avoided so as to provide increased switching speed.